1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which has an alignment mark.
2. Description of the Related Art
A photolithography method is commonly used for manufacturing a semiconductor device. In the photolithography method, a photoresist which is formed on a semiconductor wafer is exposed by using a photomask and developed for forming a circuit pattern. Then, a layer which is located under the photoresist is etched.
For example, a photomask may include a glass substrate and a circuit pattern of chrome which is formed on the glass substrate.
In the exposing step, the photomask must be aligned with the semiconductor wafer correctly. Alignment marks which are formed in the photomask and in the wafer are used for the alignment. The alignment mark which is formed in the photomask is aligned with the alignment mark which is formed in the semiconductor wafer, before performing the exposing step. The position of the alignment mark of the semiconductor wafer is detected by using a light that is reflected or diffracted from the alignment mark of the wafer. The reflected light or the diffracted light is made by emitting a light onto the alignment mark of the semiconductor wafer.
An alignment mark structure having a concave portion or a convex portion that is formed in a semiconductor wafer is disclosed in reference 1: Japanese Patent Laid-Open No. 62-128118.
An alignment mark structure having a convex portion which is formed in a semiconductor wafer, and having a light shielding film formed on the convex portion, is disclosed in reference 2: Japanese Patent Laid-Open No. 63-308916.
Recently, SOI(Silicon on Insulator) devices have been used for obtaining high performance semiconductor devices. An SOI device includes a silicon substrate, an insulating layer on the silicon substrate, and a thin silicon layer on the insulating layer. Circuit elements are formed in the thin silicon layer. SOI devices having high-speed operation and low power consumption can be obtained.
An alignment mark structure for an SOI device is disclosed in reference 3: Japanese Patent Laid-Open No. 2001-307999. The alignment mark which is disclosed in reference 3 is silicon dioxide which is embedded in the thin silicon layer.
Also, an alignment mark structure for an SOI device is disclosed in reference 4: Japanese Patent Laid-Open No. 2002-353120. The alignment mark which is disclosed in reference 4 is a concave portion which penetrates to the silicon substrate.
Recently however, a thickness of the thin silicon layer has been reduced for inhibiting a short channel effect of a transistor which is formed in the SOI substrate. As a result, a depth of an alignment mark which is formed in the thin silicon layer is not enough for detecting. Also, the alignment mark which is formed in the thin silicon layer might be removed in a manufacturing step.